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This next-generation design is called “gate-all-around.” With new materials, and redesigned manufacturing tools that cost tens of millions each, the new gates accomplish one thing: They control the flow of electricity more tightly by each transistor. Modern chips can have upwards of 30 billion transistors on a single device, and in some cases tens of billions more. In 2025, Gartner expects chip manufacturers to generate roughly $ 5 billion in revenue from new technology, up from nothing last year.

Chip companies must deliver substantially more computing horsepower every year to get a version of the future that has been promised by the tech titans. Doing so requires the chip construction of some of the most complex, expensive manufacturing equipment on the planet, and even more creative ways to improve the fundamental aspects of development. That means making already atomic-sized features even smaller. This process, loosely described as Moore’s law, has kept the chip industry humming for a half-century, but it’s getting harder.

“The rate at which we’re shrinking is sure to slow down, big time,” said Applied Materials Vice President Kevin Moraes.

Chip manufacturers improve high-volume production and performance with a combination of advanced tools such as extreme ultraviolet lithography machines and techniques that help squeeze more features onto each piece of silicon. Typically manufacturers tout improvements to their techniques and technologies as process nodes that use smaller and smaller nanometer numbers.

But there is another way to tackle the increasingly difficult problem of refining the basic building block of each chip: the transistor.

“Process nodes are just one measure of the progress,” said Jack Gold, principal analyst at J.Gold Associates. “I’d argue that even more important is the design of the transistors themselves, and not just the process node. To that end, Intel and others have been advising the design of the transistors, especially in the way the gates are designed. “

Better gates, faster chips

A gate is the tiny portion on which every transistor receives a transistor that receives electricity – kind of like using a garden hose on your foot to turn water on or off – in order to represent the zeros and those that make up bits of the data. But gates, like hoses, can be imperfect, and some of the electricity can slip through even with the most advanced designs.

“As you start making things smaller, you learn that there are some electrical characteristics with smaller elements that didn’t work as well as they did when they were bigger,” said FeibusTech analyst Mike Feibus. “There’s a rule of thumb that the smaller you get, the more current leakage you’re going to get, which is more heat.”

Because chipmakers know some electricity will evade the gate, it will continue to shrink to achieve the power consumption and performance expected of new designs. And to build more efficient gates and transistors that generate less power, chipmakers spend billions of dollars on the next, better way to develop them.

“Gate-all-around-based designs will have significantly better performance and efficiency than [existing] designs, likely shifting the competitive position for many high-performance products, “said MLCommons Executive Director David Kanter.

Surrounding all four sides of a transistor with a part of the material instead of the current three-sided design allows the gate to better regulate the flow of electricity. At the atomic scale chips operate, having better control over the flow of electricity gives designers new options: most importantly, making them even smaller.

Smaller transistors allow designers to squeeze more of them onto a single chip and adding more of these tiny features roughly translates to an improvement in the chip’s ability to perform calculations.

“With better heat and power characteristics, that means you can turn up the juice – with all else being equal – you will have higher clock rates and you shouldn’t need exotic cooling for high-performance designs, so that can cut costs, “Feibus said.

The manufacturer that successfully deploys the new generation of gate tech in high-volume production will be able to manufacture chips with a leap in computing horsepower that is impossible with the current process technology.

Fastest out of the gate

All three of the largest chip manufacturers are trying to figure out how to take advantage of this promising technology. This issue is not producing a batch of chips with the new feature; It is producing hundreds of thousands, or millions of chips, at the scale at which the most advanced technologies are needed.

Samsung may have a leg up. One of the company’s executives, Kinam Kim, co-authored an early technical paper about the new gate technology nearly 20 years ago. The company was one of the earliest to commit to producing next-generation gates, discussing its path to the tech in 2017. In April, Samsung said the company was on track to produce chips at high volume with new gates this year.

However, there is reason to be skeptical of its progress. Samsung, which did not return a request for comment, has widely reported problems with its latest manufacturing process, producing a sufficient number of working chips and has pushed back its planned launch date for the new gates several times, according to Gartner chips analyst Gaurav Gupta.

So even if the company rolls out certain chips on its new design, it may not be a viable option for its high-volume customers who demand reliability – a six-month delay will launch a new iPhone to disastrous Apple’s business, for Example:

“Samsung has always been saying they will be the first to gate-all-around at three nanometers,” Gupta said. “And they have been pushing it – for the next six months, [another] six months more, [another] six months. They’re saying now they are expecting it by the end of the year. “

Intel says its current plans call for the technology to roll out in 2024 for high-volume customers. There is reason for skepticism with Intel’s efforts too; The company went through years of delays over the last several generations of manufacturing improvements. It was also the last to adopt the EUV lithography tech that is widely viewed as necessary for future improvements. An Intel spokesperson said the company remained on track to hit its roadmap goals.

But Intel was the first company to successfully make chips at high volume with the current generation of gates, which suggests that it has technical institutional knowledge to do it again. Under CEO Pat Gelsinger, the business has a far clearer direction than the years of dysfunction that preceded him. Still, Intel has a lot to prove, and part of Gelsinger’s plan includes what Gupta described as a “very aggressive” strategy to regain its manufacturing leadership.

As it now stands, TSMC will be the last major manufacturer to move to new gate technology. Executives are tight-lipped, and the company has not responded to a request for comment, but TSMC has announced that it plans to roll it out sometime in 2025. People familiar with the company’s operations said that overall, TSMC is running conservatively. Business that prefers to avoid risks, if at all possible, and moving to a new, unproven gate technology is a big risk.

But the new gates may matter less to TSMC than its rivals. Most of its customers buy smartphone chips, and the company has proven that it can make them with the EUV tools that Intel and Samsung have struggled to deploy. As a result, TSMC may be able to use other techniques for the time being to outperform its silicon until it can ship new gate designs.

“The thing is, it’s all about power and performance, and you see 90% -plus of customers at advanced nodes in the foundry business with TSMC,” Gupta said, adding that if TSMC’s manufacturing using existing gate technology is superior to Samsung’s, TSMC won’t lose customers.

Sticking with the current generation of transistors has its advantages for chip designers too. New gates need some aspects of chip designs to get scrapped, and industry analysts said that a chip with new gates could easily exceed two or three years. So if a chipmaker such as Qualcomm, AMD or Nvidia were to make a bet that the new gates could make this year, and that doesn’t happen, they could be badly hurt.

“They call it a bleeding edge for a reason,” Feibus said. “Sometimes you get cut up.”

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